Field
The embodiments herein generally relate to a fabrication process for forming a flowable dielectric layer for use in a lithographic multi-patterning fabrication process.
Description of the Background Art
Reliably producing submicron and smaller features is one of the key requirements of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, with the continued miniaturization of circuit technology, the dimensions of the size and pitch of circuit features, such as interconnects, have placed additional demands on processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise imaging and placement of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is critical to further increases in device and interconnect density. Additionally, forming sub-micron size features and interconnects with reduced waste of intermediate materials, such as resists and hardmask materials, is desired.
As circuit densities increase for next generation devices, the width or pitch of interconnects, such as vias, trenches, contacts, devices, gates and other features, as well as the dielectric materials there between, are decreasing to 45 nm and 32 nm dimensions and beyond. As device scaling was extended to further below the resolution limit of the lithography scanners, multi-patterning was employed to enable meeting the feature density requirements of today's integrated devices. Multi-patterning is a process of performing several resist coating, lithographic patterning, and etching operations to ultimately pattern a film layer in multiple steps. When combined, the overlapping pattern operations form the features in an underlying hardmask layer, which when fully patterned, may be used to pattern an underlying layer, or serve as an implant or diffusion mask.
In one example, multiple patterning processes are widely employed in forming small features in a hardmask layer. Self-aligned double patterning (SADP) is a double patterning process used for extending the capabilities of photolithographic techniques beyond the minimum pitch. FIG. 1 depicts an example of a conventional prior art cycle 100 for a self-aligned double patterning (SADP) or self-aligned triple patterning (SATP) or even self-aligned quadruple patterning (SAQP) used to etch a hardmask layer. The conventional cycle 100 is depicted in snapshots from FIG. 1A-FIG. 1D, which are depictions of the same portions of the substrate as processing thereof progresses. In the example, a low-K layer 103 is disposed on a substrate 101. A hardmask layer 105 may be disposed on the low-K layer 102 with a patterned structure 108 (e.g., a structure patterned formed by a dielectric layer, a photoresist layer or any suitable materials for patterning) formed thereover, defining openings 118 therein. It is noted that between the patterned structure 108 and the hardmask layer 105, additional sacrificial layers may be formed to assist patterning the underlying layers. In FIG. 1B, a spacer layer 126 may be formed conformally on sidewalls 111 and a top surface 109 of the patterning structure 108 to further reduce dimensions of the opening 118 (in FIG. 1) to openings 125. In FIG. 1C, an etching process is performed to etch a portion of the spacer layer 126 from the substrate 101 until the top surface 109 of the patterned structure 108 is exposed and a surface of the underlying hardmask layer 105 is exposed. In FIG. 1D, a final etching process is performed to remove the patterned structure 108 from the substrate 101, leaving the spacer layer 126 defining new openings 145 with reduced dimensions in the spacer layer 116 on the substrate 101. After the hardmask layer 105 is further patterned using the patterned spacer layer 126 as an etching mask, a self-aligned double patterning (SADP) is then considered completed. In some cases, the process may be continued to form an additional spacer layer to further narrow down the dimension of the openings 145 to even narrower openings as needed. It is noted that numbers of the spacer layers may be formed as many as desired as long as the openings defined in between does not close-up and spacer layers apart defined by the openings.
During etching of the spacer layer 126 in FIG. 1C, different etching rates for different materials (e.g., patterned structures 108, the spacer layer 126 and the underlying hardmask layer 105) on the substrate 101 may result in different etching dimensions or asymmetric etching profile formed at different places of the resultant structure. In particular, after the etching process, the corners 132 of the spacer layer 126, as indicated in the circle 130, often suffer from rounded top shoulder erosion or undesired non-vertical sidewall etched profile, resulting in critical dimension (CD) loss or deformed profiles. Inaccurate critical dimension or profile deformation of the patterned structure may cause a light beam out-of focus issues, overlay errors and a significant resolution loss during the subsequent lithography exposure process. In some cases, inaccurate profile or structural dimensions may result in collapse of the device structure, eventually leading to device failure and product low yield.
Therefore, there is a need for an improved method for accurate profile control during a multi-patterned process.